INTERCONNECTION MECHANISM FOR MULTI-CORE ARCHITECTURES WITH SHARED CACHE MEMORY

This paper addresses the interconnection design issues of area, power and performance of chip multi processors with shared cache memory. It shows that having shared cache memory contributes a lot to an improved performance, but typical interconnection between cores and the shared cache using crossbar occupies most of the chip area and consumes a lot of power and also does not scale efficiently with increased number of cores. New interconnection mechanisms are needed to address these issues. This research suggests an architectural paradigm in an attempt to gain the advantages of having shared cache with the avoidance of penalty imposed by the crossbar interconnect. The proposed architecture achieves smaller area occupation allowing more space to add additional cache memory. It also achieves better power consumption compared to the existing crossbar architecture about 60% of the power consumed by the crossbar.