LOW POWER FDWT AND IDWT ARCHITECTURES FOR EMBEDDED APPLICATIONS

Nowadays, a substantial portion of wireless data consists of images. Widespread use of mobile devices and wireless sensors require algorithms that can comply with very limited computational power and memory. This paper introduces a low-complexity algorithm for image encoding, decoding using wavelets. The application area takes place in low-power, computationally constrained handheld portable devices, thus the power consumption and complexity of the processing algorithms should remain at a minimum level. Under this context, we choose to employ the discrete wavelet transform (DWT) with the hypothesized Haar function being the mother wavelet function, as our principal analysis method. The DWT algorithm consists of Forward DWT (FDWT) and Inverse DWT (IDWT). In this paper, a flexible architecture of multi-level decomposition Haar Wavelet Transform HWT is proposed for hardware acceleration of image compression. This architecture of HWT is described and synthesized with the VHDL based methodology. The design can be accommodated on any targeting )FPGA device( with slight changes. Simulations have been carried out using various gray scale images and capable of any levels of decomposition. Synthesis procedure shows that the design frequency amounts to 50MHz. The utilized logic and register elements of the architecture are 700 slices (only 2%) usage from 33216 slices and the architecture consumes only 0.033 W. The feasible physical layout of this low power design helps the hardware module to be implemented in many portable and embedded applications.