Modelling and Simulation of Baseband Processor for UHF RFID Reader on FPGA

A baseband processor of UHF RFID reader that presented in this paper is based on International Organization for Standardization and International Electrotechnical Commission (ISO/IEC 18000-6) protocol. The protocol also known Electronic Product Code (EPC) Class-1 Generation-2 Radio Frequency Identification (RFID) protocol. The baseband processor consists of PIE encoder, FM0 decoder and Miller decoder. The behavior of the PIE encoder, FM0 decoder and Miller decoder architecture is realized by derivation of Verilog Hardware Description Language (HDL) code in Quartus II software. Utilizing the ModelSim- Altera, the encoder and decoder architecture is simulated to observe its functionality. The designing of the encoder and decoder is intended for uses in Ultra High Frequency (UHF) RFID passive interrogator.