Performance Optimization of an Electrostatically Doped Staggered Type Heterojunction Tunnel Field Effect Transistor with High Switching Speed and Improved Tunneling Rate

In this paper, we demonstrate an electrostatically doped junctionless tunnel field effect transistor which is composed of a staggered band alignment at the heterojunction. The proposed structure reduces the tunneling barrier width to have a higher on-sate current using Ge/GaAs heterojunction at the source-channel interface. Due to the employment of electrostatically doped strategy for creating p+-n+ tunneling junction, the introduced device has low temperature simple fabrication process. The device has on-state current of 1.5×10-4 (A/μm), subthreshold swing of 5.15 mV/dec and on/off current ratio of 1.56×1010, manifesting the design of a fast switching device. In addition, statistical analysis is conducted to investigate the sensitivity of device performance with respect to the variation of critical design parameters. The results demonstrate that gate workfunction and polarity gate bias are fundamental design parameters and optimum value should be determined for them to assess efficient device performance