Design of MOESI protocol for multicore processors based on FPGA

Today's multi-core processors are built by all processor manufacturers for computers, cell phones, and other embedded systems. For all computer engineers, designing and researching the hardware architecture of multicore systems is critical. The type of cache coherence protocol employed on a multi-core computer has a direct impact on execution time, latency, and power consumption. Because it is a good example of a CPU, a 32-bit MIPS processor was chosen. With the addition of our prior work, an advanced special circuit was created using VHDL coding and ISE Xilinx software to implement it. One protocol was utilized in this design, the MOESI (Modify, Owned, Exclusive, Shared, and Invalid) protocol. The result of the test was obtained using a test bench, and they revealed that all of the protocols' states were operational.