A low power 10-bit ash analog-to-digital converter with divide and collate subranging conversion scheme

Sampling rate plays a key role in wireless applications in a very high-frequency range. Flash Analog-to-Digital Converter (ADC) outperforms slow converters in this regard, but is bulky at high resolutions. A state-of-the-art Divide and Collate (DnC) algorithm is proposed to design the ash ADC at subranging levels. The oset voltage is kept at a minimum through the comparators used for novel coarse and ne conversions, separately. The kick-back noise is also reduced using sample and hold switches at the input. The 10 bit ADC architecture is designed with 45 nm CMOS technology and analyzed in the SPECTRE environment. A minor variation in the transconductance with temperature is observed and, consequently, the offset drift with temperature is found to be 0.015 mV/fC. The design improves the Integrated Non-Linearity (INL) by 0.42 LSB and Differential Non-Linearity (DNL) by 0.3 LSB. Signal-to-Noise-and-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) are 51.8 dB and 62 dB, respectively, in the frequency range at the Nyquist rate with a supply voltage of 1 V and input frequency of 500 MHz. The subranging scheme minimizes the comparator requirements, which is re ected in the 44%reduction of the power dissipation.