Title of article :
Cascaded Multilevel Inverters with Reduced Structures Based on a Recently Proposed Basic Units: Implementing a 147-level Inverter.
Author/Authors :
Mojibian, M. J Department of Electrical Engineering - K. N. Toosi University of Technology, Tehran , Tavakoli Bina, M Department of Electrical Engineering - K. N. Toosi University of Technology, Tehran , Eskandari, B Department of Electrical Engineering - Malayer University, Malayer
Abstract :
A multilevel inverter is capable of generating high-quality stepwise pseudo-sinusoidal
voltage with low THD , applicable to high-power and high-voltage systems. These types of topologies
may require a large number of switches and power supplies. This leads to much cost, large size, and
complicated control algorithms. Thus, newer topologies are being proposed to decrease the number
of power electronic devices for a large number of levels in output voltage. Recently, a new multilevel
inverter has been reported in the literature to reduce component count. Its structure requires a lower
number of active switches as compared to the existing ones. The available literature presents a
generalization of the topology with an especial asymmetrical sources ratio, but no investigations are
made for other symmetrical or asymmetrical sources ratio with cascaded configurations. This study
presents a comprehensive analysis of cascaded topologies with the proposed basic units. The topology
is analysed for both symmetric and asymmetric DC source configurations. Also, two algorithms for
asymmetric source configuration suitable for cascaded structures are proposed. Moreover, the design
and simulation of a 147-level inverter are presented under an optimal number of DC sources and power
switches. Furthermore, experimental validation is performed by implementing a laboratory prototype.
Keywords :
Asymmetrical DC Sources , Multilevel Inverter , Packed U cell , Reduced Structures
Journal title :
AUT Journal of Electrical Engineering