Author/Authors :
Purwiyanti, Sri Shizuoka University - Research Institute of Electronics, Japan , Purwiyanti, Sri university of indonesia - Faculty of Engineering - Department of Electrical Engineering, Indonesia , Udhiarto, Arief university of indonesia - Faculty of Engineering - Department of Electrical Engineering, Indonesia , Udhiarto, Arief Shizuoka University - Research Institute of Electronics, Japan , Moraru, Daniel Shizuoka University - Research Institute of Electronics, Japan , Mizuno, Takeshi Shizuoka University - Research Institute of Electronics, Japan , Hartanto, Djoko university of indonesia - Faculty of Engineering - Department of Electrical Engineering, Indonesia , Tabe, Michiharu Shizuoka University - Research Institute of Electronics, Japan
Abstract :
As electronic device dimensions are continuously reduced, applied bias conditions significantly change and the transport mechanisms must be reconsidered. Tunneling devices are promising for scaled-down electronics because of expected high-speed operation and relatively low bias. In this work, we investigated the tunneling features in silicon-oninsulator lateral nanowire pn junction and pin junction devices. By controlling the substrate voltage, tunneling features can be observed in the electrical characteristics. We found that the minimum substrate voltage required for tunneling to occur in pn junctions is higher as compared with pin junctions. The main cause of these effects relies in the difference between the doping profiles, since the pn junctions contain a co-doped region, while the pin junctions contain an i-layer.
Keywords :
nanowire , pn junction , silicon , tunneling
