Low Power Soft-Error Hardened Latch Implemented by Carbon Nanotube Field-Effect Transistors

A soft error hardened latch is designed, which is based on carbon nanotube field-effect transistors (CNTFETs). The nanoscale circuits are more susceptible to transient or soft errors due to reduced stored charge in their sensitive nodes. Hence, an energy efficient design is a significant challenge, particularly for storage elements like latches. The proposed hardened latch consists of a Schmitt trigger circuit to mask the transient errors, a memory cell, and a C-element with an inverter at its output. The delay element followed by a C-element and a memory cell structure filters single event transient (SET) effectively and has improved robustness against single event upset (SEU). CNTFETs are substituted to gain all the benefits of nanotubes, such as robustness, temperature stability, high speed, and low power consumption. The implementation results in 32nm technology indicate a power consumption of 11.33nW for the supply voltage of 0.9V. The designed latch has low power consumption and lower power-delay product (PDP) concerning the design in CMOS technology. Compared to reported CNTFET latches, the simulation results indicate that, in addition to lower area requirement the proposed latch is more resistant to energetic particles strike than other similar latches and the rise and fall time of the proposed structure is between 12 to 15 ps in different conditions.