Author/Authors :
Rahimi, Morteza Department of Electrical Engineering - Sadjad University of Technology, Mashhad, Iran , Golmakani, Abbas Department of Electrical Engineering - Sadjad University of Technology, Mashhad, Iran , Heydari, Mohammad Ali Department of Electrical Engineering - Sadjad University of Technology, Mashhad, Iran , Mesgarof, Mohammad Hossein Department of Electrical Engineering - Sadjad University of Technology, Mashhad, Iran
Abstract :
A 10 bit Low power 666KS/s successive approximation register is presented. Monotonic capacitor-switching has been
employed to reduce the switching energy power and total capacitance by 81% and 50% respectively. The ADC
achieves an SNDR of 53.6 dB and ENOB of 8.61, while the power consumption and supply voltage are 0.83mW and
1.2V respectively. all simulations are carried out using cadence simulating software in 0.18um technology.
Keywords :
Analog-to-digital Converter , Successive Approximation Register , Energy Efficient , Monotonic Switching , Comparator , ENOB , SNDR
