An Ultra-Low Power Ternary Multi-Digit Adder Applies GDI Method for Binary Operations

Background and Objectives: A novel low-power and low-delay multi-digit ternary adder is presented in this paper which is implemented in carbon nanotube field effect transistor (CNTFET) technology. Methods: In the proposed design, CNTFET technology is used where reducing the power consumption is the main priority. A CNTFET’s geometry directly determines the threshold voltage. In this architecture, at each stage, a half adder is applied to generate the intermediate binary signals which are called half-sum (HS) and half-carry (HC). To implement the binary operations of the design, the gate diffusion input (GDI) method is applied. A significant reduction of the power consumption is achieved while the PDP is improved. Results: The proposed designs are simulated in synopsis HSPICE simulator. The Stanford 32 nm CNTFET technology is applied while the power supply is 0.9 v and the simulation is performed at room temperature. In this case, the pitch value of 20nm are chosen where the number of the tubes taken are 3. In this work a GDI based sum generator and a low-power encoder are used to calculate the final sum value of each stage. Furthermore, the proposed carry generation/propagation block results in a remarkable reduction of the overall propagation delay time. The simulation reveals a significant improvement in terms of the power consumption (up to 27%), the PDP (up to 41%) and the FO4 delay (up to 20%). Conclusion: An efficient CNTFET based multi-digit ternary adder has been presented in this paper. The Synopsis HSPICE simulator is used where Stanford 32 nm CNTFET model are applied to simulate the design. According to the results, a significant saving in average power consumption is achieved where the power-delay product (PDP) is improved by 41% compared to the best existing design.