Fault Tolerant Nanoscale Structures and Related Delay

Redundancy is a method in the system for designing fault tolerant structure with the Nanoscale gate in electronic systems. Until now, many ways are represented for this purpose, which increases complexity or decreases the system's reliability. In this paper, we compare two methods for designing a fault-tolerant structure with Nanoscale gates. These ways are NAND Multiplexing (NM) and Averaging Cells (AC). The results of simulation that evaluate the area cost and reliability of the gates indicates that NM based gates are more reliable than AC gates when the error probabilities of the circuit parts are lower than 0.003. However, when this value is exceeded (which is expected for electronic nanotechnologies), AC gates are more reliable at a lower area cost. In this paper, we show comparing the NM and the AC in the aspect of the delay parameter. It indicates that the AC method has a constant delay, but the NM system's delay will rise with increasing redundancy. As a result, the AC method's overhead for designing a fault-tolerant system with the Nanoscale gate is lower than the NM method in the aspect of the area and delay time with better reliability