Single-ended 6T SRAM Cell with Low Power/Energy Consumption and High Stability

In this paper, we propose 6T cell with single-ended characteristics to achieve an improved stability, decrease energy consumption, and decrease leakage power. The cell is compared with strong 10 and 12 transistor structures with good and excellent specifications. However, the above structure is designed to have the best parameters with low size and a minimum number of transistors that reduce the size of the cell. In some parameters, such as the write noise margin, the structure has the best merits in comparison with other structures, even higher than the structures of 12 and 10 transistors. The write operation is enhanced by cutting the pull-down path to the storage node to be written as “1”; the read operation is performed without cutting the pull-down path. At VDD=0.4V, the static power, read margin, write margin, read energy, and write energy of the proposed structure are superior by 33%, 50%, 215%, 9%, and 5%, respectively, in contrast to the traditional 6T. The Electrical Quality Metric (EQM) parameter has been improved about ten times compared with the standard 6T structure, showing that the value of the new structure has been introduced. A Monte Carlo simulation of 5,000 read and write yields in the 32nm technology revealed that our cell has a 2x and 3.4x higher yield than the typical 6T cell. Consequently, the proposed 6T cell is an appropriate option for applications requiring low energy and high robustness.