Low-Power High-Frequency Phase Frequency Detector Based on Carbon Nano-Tube FET with Zero Dead-Zone for CPPLL

Achieving low power consumption and low delay are the most important goals that efforts have been made to reach. In this paper, the process of designing and optimizing the Phase Frequency Detector (PFD) performance at the integrated circuits (IC) level has been proposed using carbon nanotubes. In the proposed method, by using carbon nanotube transistors, improvements have been made in the output parameters of the phase detector. Failure to use flip-flops and the simple circuit structure will significantly increase speed and reduce power consumption. Post-layout simulation for 180nm CMOS technology and simulation results for 32nm Carbon Nanotube Field-Effect Transistor (CNTFET) technology is presented. The proposed CMOS 28T phase detector circuit, by injecting 30mV peak-topeak power supply noise has 5× better operating frequency of the conventional circuit, and it has a 10% improvement in power consumption of the conventional one. Also, with carbon nanotubes, the frequency has increased 4 times, and the power consumption has improved significantly. In this case, the power consumption is 1.76 microwatts, and the operating frequency is 20 GHz. Open-loop design and elimination of the reset path, and attention to delays to remove the dead zone are the proposed circuit s top features compared with the traditional design methods.