Title of article
Oversampling ΣΔ Analog-to-Digital Converters Modeling Based on VHDL
Author/Authors
Robert Baraniecki، نويسنده , , Przemys?aw Dabrowski and Konrad Hejn، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 1998
Pages
9
From page
101
To page
109
Keywords
Sigma-delta modulator , decimator , VHDL , behavioral modeling and simulation , RTL synthesis
Journal title
Analog Integrated Circuits and Signal Processing
Serial Year
1998
Journal title
Analog Integrated Circuits and Signal Processing
Record number
366881
Link To Document