Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial

Xiaoyan Ye and Xiaodong Yang، نويسنده , , Chung-Kuan Cheng، نويسنده , , Walter H. Ku and Robert Carragher ، نويسنده ,

روزنامه با شماره پیاپی سال 2002

16

193

208

Model Order Reduction , interconnect , Inductance , Timing , deep-submicron , VLSI

Analog Integrated Circuits and Signal Processing

2002

Analog Integrated Circuits and Signal Processing

367211