Title of article
A Fully Integrated CMOS Phase-Locked Loop with 30 MHz to 2 GHz Locking Range and ±35 ps Jitter
Author/Authors
Chao Xu، نويسنده , , Winslow Sargeant، نويسنده , , Kenneth R. Laker and Jan Van der Spiegel ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2003
Pages
7
From page
91
To page
97
Keywords
Jitter , dual loop architecture , clock data recovery , phase-locked loop (PLL)
Journal title
Analog Integrated Circuits and Signal Processing
Serial Year
2003
Journal title
Analog Integrated Circuits and Signal Processing
Record number
367348
Link To Document