Title of article
An Integrated CAD Methodology for Yield Enhancement of VLSI CMOS Circuits Including Statistical Device Variations
Author/Authors
Massimo Conti، نويسنده , , Paolo Crippa، نويسنده , , Simone Orcioni، نويسنده , , Marcello Pesare، نويسنده , , Simone Orcioni and Claudio Turchetti ، نويسنده , , Loris Vendrame and Silvia Lucherini ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2003
Pages
18
From page
85
To page
102
Keywords
parametric yield , device mismatch , optimization , statistical process variations , CAD tool
Journal title
Analog Integrated Circuits and Signal Processing
Serial Year
2003
Journal title
Analog Integrated Circuits and Signal Processing
Record number
367373
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