Title of article
A Novel Dual-Modulus 2.8 GHz Divide-by-127/128 Prescaler Using Pull Down Transistor in 0.35 μ m CMOS Technology
Author/Authors
Ram Singh Rana ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2005
Pages
5
From page
191
To page
195
Keywords
prescaler - CMOS - dual-modulus - filp-flop - PLL - counter
Journal title
Analog Integrated Circuits and Signal Processing
Serial Year
2005
Journal title
Analog Integrated Circuits and Signal Processing
Record number
367490
Link To Document