Title of article
Parallel-pipeline 8×8 forward 2-D ICT processor chip for image coding
Author/Authors
G. A. Ruiz، نويسنده , , J. A. Michell، نويسنده , , and A. M. Bur?n، نويسنده ,
Issue Information
روزنامه با شماره پیاپی 1 سال 2005
Pages
10
From page
714
To page
723
Keywords
image compression , Integer cosine transform , parallel pipelined architectures , VLSI. , multiplication free DCT
Journal title
IEEE TRANSACTIONS ON SIGNAL PROCESSING
Serial Year
2005
Journal title
IEEE TRANSACTIONS ON SIGNAL PROCESSING
Record number
388903
Link To Document