Author/Authors :
McShane، نويسنده , , E.، نويسنده , , Trivedi، نويسنده , , M.، نويسنده , , Ying Xu، نويسنده , , Khandelwal، نويسنده , , P.، نويسنده , , Mulay، S نويسنده , , A.، نويسنده , , Shenai، K. نويسنده , , K.، نويسنده ,
Abstract :
Consumer demand for portable computing and mobile wireless communications will continue to drive development of functionally integrated, ultra-low-power systems on a chip. CMOS bulk processing is likely to emerge as the foundation of mixed-signal, ultra-low-power ICs because of its inherent advantages for low-power logic and flexibility in RF applications. To successfully meet time-to-market goals and shrink product-development cycles, computer-aided design tools must guide a design from conceptualization to physical implementation. Estimates of floorplan arrangement and interconnect and package parasitics are necessary early in the design flow, since these undesirable contributions can dominate over the intrinsic device parasitics