Global (interconnect) warming

This article presents a comprehensive analysis of the thermal effects in advanced high-performance VLSI interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge (ESD). Technology (Cu, low-k, etc.) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration (EM) reliability, have been analyzed simultaneously, which have important implications for providing robust and aggressive deep sub-micron (DSM) interconnect design guidelines. The analysis takes into account the effects of increasing interconnect (Cu) resistivity with decreasing line dimensions and the effect of a finite barrier metal thickness. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the global-tier signal lines are investigated. Finally, the reliability implications for minimum-sized vias in optimally buffered signal nets will also be quantified