Understanding VLSI bit serial multipliers

he efficient design of bit serial multipliers is necessary in many applications areas as diverse as digital communications and the implementation of artificial neural networks. Because of these applications, bit serial architectures are a part of courses in computer arithmetic, very large scale integration (VLSI) architectures, and digital signal processing. Comprehensive descriptions for three bit serial algorithms for signed multiplication are presented. The primary difference among the three algorithms is in the recoding of the multipliers. Each bit serial multiplier is systematically derived from its equivalent parallel multiplier found in textbooks. Furthermore, complete CMOS layouts for the three multipliers are constructed, simulated, and compared.