A hardware efficient control of memory addressing for high-performance FFT processors

The conventional memory organization of fast Fourier transform (FFT) processors is based on Cohen’s scheme. Compared with this scheme, our scheme reduces the hardware complexity of address generation by about 50% while improving the memory access speed. Much power consumption in memory is saved since only half of the memory is activated during memory access, and the number of coefficient access is reduced to a minimum by using a new ordering of FFT butterflies. Therefore, the new scheme is a superior solution to constructing high-performance FFT processors.