An efficient design for one-dimensional discrete Hartley transform using parallel additions

This paper presents a new efficient design for the onedimensional (1-D) any-length discrete Hartley transform (DHT). Using the similar idea to the Chirp-Z transform, an algorithm that can formulate the 1-D any-length DHT as cyclic convolutions is developed. This algorithm owns higher flexibility in the transform length as compared with the existing approaches for prime length DHT or power-of-two DHT designs. Moreover, the proposed design exploits the good feature of cyclic convolution and uses parallel adders instead of multipliers in the hardware realization. The presented design not only possesses low hardware cost but also owns low input/output (I/O) cost, high computing speeds, and flexibility in transform length.