Title of article :
How ATE Planning Affects LSI Manufacturing Cost
Author/Authors :
Koji Nakamae Homare Sakamoto Hiromu Fujioka ، نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 1996
Pages :
8
From page :
66
To page :
73
Abstract :
To analyze the effects of automatic test equipment planning on total LSI manufacturing cost cost per chip, we simulate manufacturing cost by combining discrete event simulation and detailed parametric models of the LSI manufacturing system. This combination provides a more realistic evaluation than previous methods. For our example of ATE planning, we optimize the distribution of LSI testers between the wafer test process and final test process for cost per chip
Journal title :
IEEE Design and Test of Computers
Serial Year :
1996
Journal title :
IEEE Design and Test of Computers
Record number :
431112
Link To Document :
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