Noise Generation and Coupling Mechanisms in Deep-Submicron ICs

On-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity. Selecting adequate test techniques depends on the circuit, its implementation, and the possible physical failures and parasitic coupling models. This new demand for test technology practices precipitated the investigation of dl/dt and dV/dt noise generation and propagation mechanisms