Title of article
ITC Highlights Gordon W. Roberts, McGill University Robert C. Aitken, Artisan Components pp. 55-57 Embedded Deterministic Test for Low-Cost Manufacturing Janusz Rajski, Mentor Graphics Mark Kassab, Mentor Graphics Nilanjan Mukherjee, Mentor Graph
Author/Authors
Janusz Rajski، نويسنده , , Mentor Graphics Mark Kassab، نويسنده , , Mentor Graphics Nilanjan Mukherjee، نويسنده , , Mentor Graphics Nagesh Tamarapalli، نويسنده , , Mentor Graphics Jerzy Tyszer، نويسنده , , Poznan University of Technology Jun Qian، نويسنده , , Cisco Systems ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2003
Pages
9
From page
58
To page
66
Abstract
You have probably heard that BIST takes too long and its fault coverage is low, and that deterministic test requires too many patterns. This article shows how on-chip compression and decompression techniques provide high fault coverage with low test times.
Journal title
IEEE Design and Test of Computers
Serial Year
2003
Journal title
IEEE Design and Test of Computers
Record number
431456
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