Title of article :
Safety Property Verification Using Sequential SAT and Bounded Model Checking
Author/Authors :
Ganapathy Parthasarathy، نويسنده , , University of California، نويسنده , , Santa Barbara Madhu K. Iyer، نويسنده , , University of California، نويسنده , , Santa Barbara Kwang-Ting (Tim) Cheng، نويسنده , , University of California، نويسنده , , Santa Barbara Li-C. Wang، نويسنده , , University of California، نويسنده , , Santa Barbara ، نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2004
Pages :
12
From page :
132
To page :
143
Abstract :
Model checkers verify properties of safety- or business-critical systems. The main idea behind model checking is to convert a designʹs verification into a problem of checking key design properties expressed as a set of temporal logic formulas. The graph representing the designʹs state space then becomes the basis for testing these formulasʹ satisfiability (SAT). This divide-and-conquer approach provides an overall test for design correctness. We describe a method for checking safety properties using sequential SAT. SSAT can efficiently prove true properties by harnessing the power of bounded model checking (BMC) using SAT, but without the need for a pre-computed correctness threshold. Using a standard set of benchmarks, we conducted experiments to compare the runtime behavior of SSAT with BMC and binary decision diagrams (BDDs).
Journal title :
IEEE Design and Test of Computers
Serial Year :
2004
Journal title :
IEEE Design and Test of Computers
Record number :
431482
Link To Document :
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