Title of article :
Logic Synthesis for Manufacturability
Author/Authors :
Alessandra Nardi، نويسنده , , University of California، نويسنده , , Berkeley Alberto L. Sangiovanni-Vincentelli، نويسنده , , University of California، نويسنده , , Berkeley ، نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2004
Pages :
8
From page :
192
To page :
199
Abstract :
Design optimization during synthesis is for area and/or performance while optimization for yield occurs at the layout level. To obtain abstraction level for yield optimization by introducing an interesting approach to yield-driven logic synthesis. Design for manufacturability denotes all techniques designers use to estimate and control yield and robustness during the design phase, prior to manufacturing.
Journal title :
IEEE Design and Test of Computers
Serial Year :
2004
Journal title :
IEEE Design and Test of Computers
Record number :
431495
Link To Document :
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