Author/Authors :
T.M. Mak، نويسنده , , Intel
Angela Krstic، نويسنده , , University of California، نويسنده , , Santa Barbara
Kwang-Ting (Tim) Cheng، نويسنده , , University of California، نويسنده , , Santa Barbara
Li-C. Wang، نويسنده , , University of California، نويسنده , , Santa Barbara
، نويسنده ,
Abstract :
Less predictable path delays and many paths with delays close to the clock period are the main trends affecting the delay testability of deep-submicron designs. We examine the challenges in meeting the quality requirements of gigascale integration, and explore functional testing as well as statistical models and methods that could alleviate some of those problems.
