Title of article
DFT for Delay Fault Testing of High-Performance Digital Circuits
Author/Authors
Bhaskar Chatterjee، نويسنده , , University of Waterloo Manoj Sachdev، نويسنده , , University of Waterloo Ali Keshavarzi، نويسنده , , Intel Laboratories ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2004
Pages
11
From page
248
To page
258
Abstract
Timing-only parametric defects are a major source of failures and test escapes in modern ICs. A DFT technique using compound domino logic gates with footer transistors uncovers these hard-to-detect defects with minimal performance and power overheads.
Journal title
IEEE Design and Test of Computers
Serial Year
2004
Journal title
IEEE Design and Test of Computers
Record number
431501
Link To Document