TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification

This hybrid dynamic simulation scheme implements part of the simulator in software running on a processor and maps the rest onto a programmable hardware accelerator. An algorithm for hardware synthesis of behavioral testbenches enables better partitions, resulting in lower communication costs between the two components. TPartition improves the performance of hardware accelerated simulation without a designerʹs remodeling effort and without losing compatibility with the original testbench.