Author/Authors :
Fernanda Gusmao de Lima Kastensmidt، نويسنده , , State University of Rio Grande do Sul
Gustavo Neuberger، نويسنده , , Federal University of Rio Grande do Sul
Renato Fernandes Hentschke، نويسنده , , Federal University of Rio Grande do Sul
Luigi Carro، نويسنده , , Federal University of Rio Grande do Sul
Ricardo Reis، نويسنده , , Federal University of Rio Grande do Sul
، نويسنده ,
Abstract :
FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuitʹs operation. We present a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CEO) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques.
