Author/Authors :
Rajeev R. Rao، نويسنده , , University of Michigan، نويسنده , , Ann Arbor
David Blaauw، نويسنده , , University of Michigan، نويسنده , , Ann Arbor
Dennis Sylvester، نويسنده , , University of Michigan، نويسنده , , Ann Arbor
Anirudh Devgan، نويسنده , , Magma Design Automation
، نويسنده ,
Abstract :
Leakage current is a stringent constraint in todayʹs ASIC designs. Effective parametric yield prediction must consider leakage currentʹs dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and gate leakage currents. This model underlies an integrated approach to accurately estimating yield loss for a design with both frequency and power limits.
