Title of article
Design, Synthesis, and Test of Networks on Chips
Author/Authors
Partha Pratim Pande، نويسنده , , Washington State University Cristian Grecu، نويسنده , , University of British Columbia André Ivanov، نويسنده , , University of British Columbia Resve Saleh، نويسنده , , University of British Columbia Giovanni De Micheli، نويسنده , , Ecole Polytechnique Federale de Lausanne ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2005
Pages
10
From page
404
To page
413
Abstract
For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.
Journal title
IEEE Design and Test of Computers
Serial Year
2005
Journal title
IEEE Design and Test of Computers
Record number
431605
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