3D Chip Stack Technology Using Through-Chip Interconnects

The current technology in micro-and nano-electronics is insufficient to meet future demands for several applications. Most state-of-the-art solutions rely on so-called embedded technologies, which are both expensive and complex. One solution to the problem of integrating mixed technologies is the concept of 3D stacking. Our approach implements an epitaxial etch-stop layer for thickness control of the thinning process. Using this etch-stop layer, we can create a precise alignment of back-side vias to the landing pads in the first metal layer of the active CMOS, resulting in small via diameters and high connection densities between individual-layers of the 3D stack. Furthermore, we can use other materials, like GaAs (gallium arsenide), in combination with an epitaxial lift-off process. We use a copper-tin soldering process based on the solid-liquid interdiffusion (solid) process to create the electrical and mechanical connection between the single chip layers. Using this process, we created true multilayer stacks and tested them with respect to the static electrical properties of ohmic contacts and interchip vias. We directly incorporated these results in the design of test circuits that create tests for stuck-at failures of the interchip connections after stack assembly. This article presents a technology overview of how to achieve the goal in a 3D fabrication process. It also shows measurements for characterizing interconnects.