IC Outlier Identification Using Multiple Test Metrics

With increasing variation in parametric data, it is necessary to adopt statistical means and correlations that consider other process parameters. Determining an appropriate threshold is difficult because of the several orders of magnitude variation in fault-free IDDQ. Therefore, it is necessary to use secondary information to identify outliers. This article proposed a combination of two IDDQ test metrics for screening outlier chips by exploiting wafer-level spatial correlation. No single metric alone suffices to screen all outliers. The addition of a secondary metric also comes at the risk of additional yield loss. Maintaining stringent process control proves to be challenging for deer-submicron technologies. Therefore, understanding underlying process variables and their impact on test parameters are crucial for yield requirements. As IDDQ test loses its effectiveness, it becomes necessary to correlate multiple test metrics, and a combination of multiple outlier screening methods might be necessary. A combination of CR and NCR with other test parameters can be useful for screening low-reliability chips, and an analysis of wafer patterns can be useful in reducing the number of required vector pairs.