Title of article
Reducing Burn-in Time through High-Voltage Stress Test and Weibull Statistical Analysis
Author/Authors
Mohd Fairuz Zakaria، نويسنده , , Freescale Semiconductor، نويسنده , , Malaysia Zainal Abu Kassim، نويسنده , , Freescale Semiconductor، نويسنده , , Malaysia Melanie Po-Leen Ooi، نويسنده , , Monash University Malaysia Serge Demidenko، نويسنده , , Monash University Malaysia ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2006
Pages
11
From page
88
To page
98
Abstract
To guarantee an industry standard of reliability in ICs, manufacturers incorporate special testing techniques into the circuit manufacturing process. For most electronic devices, the specific reliability required is quite high, often producing a lifespan of several years. Testing such devices for reliability under normal operating conditions would require a very long period of time to gather the data necessary for modeling the deviceʹs failure characteristics. Under this scenario, a device might become obsolete by the time the manufacturer could guarantee its reliability. High-voltage stress testing (HVST) is common in IC manufacturing, but publications comparing it with other test and burn-in methods are scarce. This article shows that the use of HVST can dramatically reduce the amount of required burn-in.
Journal title
IEEE Design and Test of Computers
Serial Year
2006
Journal title
IEEE Design and Test of Computers
Record number
431645
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