Author/Authors :
Jeffrey E. Nelson، نويسنده , , Carnegie Mellon University
Thomas Zanon، نويسنده , , Carnegie Mellon University
Jason G. Brown، نويسنده , , Carnegie Mellon University
Osei Poku، نويسنده , , Carnegie Mellon University
R.D. (Shawn) Blanton، نويسنده , , Carnegie Mellon University
Wojciech Maly، نويسنده , , Carnegie Mellon University
Brady Benware، نويسنده , , LSI Logic
Chris Schuermyer، نويسنده , , LSI Logic
، نويسنده ,
Abstract :
Defect density and size distributions (DDSDs) are important parameters for characterizing spot defects in a process. This article addresses random spot defects, which affect all processes and currently require a heavy silicon investment to characterize and a new approach is proposed for characterizing such defects. This approach presents a system that overcomes the obstacle of silicon area overhead by using available wafer sort test results to measure critical-area yield model parameters with no additional silicon area. The results of the experiment on chips fabricated in silicon confirm the results of the simulation experiment that DDSDs measurement characterizes a process in ordinary digital circuits using only slow, structural test results from the product