Title of article
Variation-Tolerant, Power-Safe Pattern Generation
Author/Authors
V.R. Devanathan، نويسنده , , Texas Instruments India C.P. Ravikumar، نويسنده , , Texas Instruments India V. Kamakoti، نويسنده , , Department of Mathematics Indian Institute of Technology Delhi، نويسنده , , Madras ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2007
Pages
11
From page
374
To page
384
Abstract
By generating safe patterns - those that tolerate on-chip variations - this framework avoids false delay test failures. It uses power grid information and regional constraints on switching activity to minimize peak power and optimize the pattern set. Experimental results on benchmark circuits demonstrate the frameworkʹs effectiveness.
Journal title
IEEE Design and Test of Computers
Serial Year
2007
Journal title
IEEE Design and Test of Computers
Record number
431758
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