Author/Authors :
V.R. Devanathan، نويسنده , , Texas Instruments India
C.P. Ravikumar، نويسنده , , Texas Instruments India
V. Kamakoti، نويسنده , , Department of Mathematics Indian Institute of Technology Delhi، نويسنده , , Madras
، نويسنده ,
Abstract :
By generating safe patterns - those that tolerate on-chip variations - this framework avoids false delay test failures. It uses power grid information and regional constraints on switching activity to minimize peak power and optimize the pattern set. Experimental results on benchmark circuits demonstrate the frameworkʹs effectiveness.
