Well-behaved global on-chip interconnect

Global interconnects have been identified as a serious limitation to chip scaling, due to their latency and power consumption. We demonstrate a scheme to overcome these limitations, based on the utilization of upper-level metals, combined with structured communication architecture. Microwave style transmission lines in upper-level metals allow close-to-velocity-of-light delays if properly dimensioned. As an example, we demonstrate a 480-(mu)m-wide and 20-mm-long bus with a capacity of 320 Gb/s in a nearly standard 0.18-(mu)m process. The process differs from a standard process only through a somewhat thicker outer metal layer. We further illustrate how "self pre-emphasis" at the launch of a data pulse can be used to double the maximum available data rate over a wire. The proposed techniques are scalable, given that higher level metals are properly dimensioned in future processes.