Design of double-sampling(Sigma)(Delta) modulation A/D converters with bilinear integrators

Double-sampling techniques allow to double the sampling frequency of a switched capacitor (Sigma)(Delta) analog-todigital convertors without increasing the clock frequency. Unfortunately, path mismatch between the double sampling branches may cause noise folding, which could ruin the modulatorʹs performance. The fully floating double-sampling integrator is an interesting building block to be used in such a double sampling (Sigma)(Delta) modulator because its operation is tolerant to path mismatch. However, this circuit exhibits an undesired bilinear filter effect. This effectively increases the order of the modulator by one. Due to this, previously presented structures donʹt have enough freedom to fully control the modulator pole positions. In this paper, we introduce modified topologies for double-sampling(Sigma)(Delta) modulators built with bilinear integrators. We show that these architectures provide full control of the modulator pole positions and hence can be used to implement any noise transfer function. Additionally, analytical expressions are obtained for the residual folded noise.