A continuous-time (sigma)(delta) Modulator with reduced sensitivity to clock jitter through SCR feedback

This paper presents a means to overcome the high sensitivity of continuous-time sigma-delta ((sigma)(delta)) modulators to clock jitter by using a modified switched-capacitor structure with resistive element in the continuous-time feedback digital-analog converter (DAC). The reduced sensitivity to jitter is both simulated and proven by measured results from two implemented third-order modulators. Additionally, the nonideal behavior is analyzed analytically and by simulations.