An Efficient, Fully Parasitic-Aware Power Amplifier Design Optimization Tool

A methodology for the optimal parasitic-aware design of RF power amplifiers toward maximum power efficiency is presented. It is based on a template-driven simulation-based optimization approach, including the effect of all device parasitics (transistors, passives) during the sizing. The combination of expert knowledge (in the template) with a state-of-theart evolutionary algorithm results in a highly flexible and optimal sizing methodology tailored to RF circuits. Parasitic information is obtained through interaction with device profilers. The methodology is implemented in a fully featured software tool called M-DESIGN and is applied to the optimal sizing of a two-stage Class E power amplifier for maximum efficiency. The complete sizing was obtained in less than one hour of CPU time. Moreover, the constraint templates that were used are presented and discussed. An amplifier manufactured in a commercial 0.35-(mu)m5M2P CMOS process and sized using the proposed methodology shows a maximum value of 67% for the drain efficiency (DE) versus 66% simulated. Measurement results show that it works at 850 MHz and has a maximum output power of 30 dBm at 2.3 V. The poweradded efficiency (PAE) is always greater than 60% for an output power above 160 mW and a maximum PAE of 66% is achieved.