Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits

Power dissipation in sequential circuits is due to increased toggling count of Circuit underTest, which depends upon test vectors applied. If successive test vectors sequences have moretoggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flipflops results more power dissipation. To overcome this problem, one method is to use GA tohave test vectors of high fault coverage in short interval, followed by Hamming distancemanagement on test patterns. This approach is time consuming and needs more efforts. Anothermethod which is purposed in this paper is a PSO based Frame Work to optimize powerdissipation. Here target is to set the entire test vector in a frame for time period ‘T’, so that theframe consists of all those vectors strings which not only provide high fault coverage but alsoarrange vectors in frame to produce minimum toggling