Hardware Implementation Low Power High Speed FFT Core

In recent times, DSP algorithms have received increased attention due to rapid advancements in multimediacomputing and high-speed wired and wireless communications. In response to these advances, the search for novelimplementations of arithmetic-intensive circuitry has intensified. For the portability requirement in telecommunicationsystems, there is a need for low power hardware implementation of fast fourier transforms algorithm. This paper proposes thehardware implementation of low power multiplier-less radix-4 single–path delay commutator pipelined fast fourier transformprocessor architecture of sizes 16, 64 and 256 points. The multiplier-less architecture uses common sub-expression sharing toreplace complex multiplications with simpler shift and add operations. By combining a new commutator architecture and lowpower butterfly architecture with this approach power reduction is achieved. When compared with a conventional fast fouriertransform architecture based on non-booth coded wallace tree multiplier the power reduction in this implementation is 44%and 60% for 64-point and 16-point radix-4 fast fourier transforms respectively. The power dissipation is estimated usingcadence RTL compiler. The operating frequencies are 166 MHz and 200 MHz, for 64 point and 16 point fast fouriertransforms, respectively. Our implementation of the 256 point FFT architecture consumes 153 mw for an operating speed of125 MHz