Design VLSI Median Filter

A low-power and high-speed mixed-signal VLSI median filter has been developed. The binary search algorithm has been employed and the median filter circuit was built using majority voting circuits. As a result, small latency median search has been established. In order to achieve a low power operation, majority voting circuits of voltage mode of operation have been developed based on the floating gate MOS technology. An 8-b 41-input median filter circuit was designed and fabricated in 0.18-?m 2- poly 3-metal CMOS technology as a proof-of-concept chip and the operation was experimentally demonstrated. It was shown that more than 70% power reduction has been achieved as compared to our previous work employing current-mode MVC’s, while preserving the highspeed performance achieved in the work.