Structural RFIC device testing through built-in thermal monitoring

Current RFIC test practices perform system-level verification through specific functional validation. Structural testing, although widely accepted for digital and analog generic ICs, is not adopted in this domain due to the lack of appropriate fault models. Another important reason is the impossibility of embedding test-mode circuitry within the RF blocks because of parasitic component disturbances. This work discusses the feasibility of complementing functional tests with structural methods by using thermal testing. The benefits reside in the intrinsic electrical loadless property of the technique and the impact of many defects on the circuit temperature. The analysis focuses on the possibilities of detecting defects that escape functional testing, and practical implementation issues.