Digital Background Calibration for Capacitor Nonlinearity in Pipelined Analog to Digital Converter

This paper presents a digital background calibration algorithm for 1.5bit/stage analog to digital converter. The error that discussed in this paper is: capacitor nonlineary error due to MOSCAP of first stage of pielined ADC. Proposed calibration algorithm uses an 16 bit sigma-delta ADC for calibration and coefificien is updated with LMS algorithm. A 14-bit pipelined ADC is simulated by Matlab Simulink. After calibration, simulation gives a great improvement in SNDR and SFDR.